Journals

  1. Consequence-based Clustered Architecture
    Shruthi Karunakar, Rajshekar Kalayappan, Sandeep Chandran
    ACM Transactions on Architecture and Code Optimization (TACO). (Just Accepted), 2024.
  2. A Formal Approach to Accountability in Heterogeneous Systems-on-Chip
    Rajshekar Kalayappan, Smruti R. Sarangi
    IEEE Transactions on Dependable and Secure Computing (TDSC). Volume 18 Issue 6, 2021.
  3. A Survey of Cache Simulators
    Hadi Brais, Rajshekar Kalayappan, Preeti Ranjan Panda
    ACM Computing Surveys (CSUR). Volume 53 Issue 1, 2020.
  4. ChunkedTejas: A Chunking-based Approach to Parallelizing a Trace-Driven Architectural Simulator
    Rajshekar Kalayappan, Avantika Chhabra, Smruti R. Sarangi
    ACM Transactions on Modeling and Computer Simulation (TOMACS). Volume 30 Issue 3, 2020.

    Presented at ACM SIGSIM Principles of Advanced Discrete Simulation (PADS), 2022.
  5. Providing Accountability in Heterogeneous Systems-on-Chip
    Rajshekar Kalayappan, Smruti R. Sarangi
    ACM Transactions on Embedded Computing Systems (TECS). Volume 17 Issue 5, 2018.
  6. ParTejas : A Parallel Simulator for Multicore Processors
    Geetika Malhotra, Rajshekar Kalayappan, Seep Goel, Pooja Aggarwal, Abhishek Sagar, Smruti R. Sarangi
    ACM Transactions on Modeling and Computer Simulation (TOMACS). Volume 27 Issue 3, 2017.
  7. FluidCheck: A Redundant Threading-Based Approach for Reliable Execution in Many-core Processors
    Rajshekar Kalayappan, Smruti R. Sarangi
    ACM Transactions on Architecture and Code Optimization (TACO). Volume 12 Issue 4, 2016.

    Presented at European Network on High Performance and Embedded Architecture and Compilation Conference (HiPEAC'16), Prague, Czech Republic, 2016.
  8. Surveillance using non-stealthy sensors: A new intruder model
    Amitabha Bagchi, Rajshekar Kalayappan, Surabhi Sankhla
    Wiley Security and Communication Networks. Volume 7, Issue 11, 2014.
  9. A survey of checker architectures
    Rajshekar Kalayappan, Smruti R. Sarangi
    ACM Computing Surveys (CSUR). Volume 45, Issue 4, 2013.

Conferences

  1. faRM-LTL: A Domain-Specific Architecture for Flexible and Accelerated Runtime Monitoring of LTL Properties
    Amrutha Benny, Sandeep Chandran, Rajshekar Kalayappan, Ramchandra Phawade and Piyush Kurur
    24th International Conference on Runtime Verification (RV2024), Istanbul, Turkey, 2024.
  2. CASH: Criticality-Aware Split Hybrid L1 Data Cache
    Shruthi Karunakar, Meenakshi Atkade, Akash Poptani, Rajshekar Kalayappan, Sandeep Chandran
    34th ACM Great Lakes Symposium on VLSI (GLSVLSI'24), Tampa Bay Area, FL, USA, 2024.
  3. On Decomposing Complex Test Cases for Efficient Post-silicon Validation
    Harshitha C, Sundarapalli Harikrishna, Peddakotla Rohith, Sandeep Chandran, Rajshekar Kalayappan
    Asia and South Pacific Design Automation Conference (ASP-DAC’24), Incheon, South Korea, 2024.
    [Nominated for the best paper award]
  4. Enhancing the Dependability of Electronic Control Systems through Reprogrammable Runtime Verification Monitors
    Amruta Benny, Sandeep Chandran, Rajshekar Kalayappan
    Frontiers of Aerospace Systems and Technologies (FAST) 2023.
  5. SANNA: Secure Acceleration of Neural Network Applications
    Akash Poptani, Abhishek Mittal, Rishit Saiya, Rajshekar Kalayappan and Sandeep Chandran
    International Conference on VLSI Design (VLSID'23), Hyderabad, India, 2023.
  6. A Hardware Implementation of the kCAS Synchronization Primitive
    Srishty Patel, Rajshekar Kalayappan, Ishani Mahajan, Smruti R. Sarangi
    Design, Automation and Test in Europe (DATE'17), Lausanne, Switzerland, 2017.
  7. SecCheck : A Trustworthy System with Untrusted Components
    Rajshekar Kalayappan, Smruti R. Sarangi
    IEEE Computer Society Annual Symposium on VLSI (ISVLSI'16), Pittsburgh, USA, 2016.
  8. SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators
    Rajshekar Kalayappan, Smruti R. Sarangi
    IEEE Computer Society Annual Symposium on VLSI (ISVLSI'15), Montpellier, France, 2015.
  9. Tejas: A java based versatile micro-architectural simulator
    Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel, Eldhose Peter
    IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'15), Salvador, Brazil, 2015.

Patents

  1. A System-on-Chip with In-Built Mechanism and method for Identification of Faulty Components in the System-on-Chip
    Smruti R. Sarangi, Rajshekar Kalayappan. Indian patent granted: 523610.
  2. System and method for improving the performance of an architectural simulator
    Smruti R. Sarangi, Rajshekar Kalayappan, Avantika Chhabra. Indian patent granted: 547651.